This paper focuses on the effect of heterogeneous cache hierarchy in data center processors in the dark silicon era. For extreme-scale high performance computing systems, system-wide power consumption has been identified as one of the key constraints. As energy consumption becomes a key issue for operation and maintenance of cloud data centers, cloud computing providers are becoming significantly concerned. Emerging non-volatile memory technologies are favorable replacement for conventional memory. Here, we employ a nonvolatile memory called spin-transfer torque random access memory (STT-RAM) as an on-chip L2 cache to obtain lower energy compared to conventional L2 caches, like SRAM. High density, fast read access, near-zero leakage power and non-volatility make STT-RAM a significant technology for on-chip memories. In order to decrease memory energy consumption, it is required to address both the leakage and dynamic energy. Previous studies have mainly studied specific schemes based on common applications and do not provide a thorough analysis of emerging scale-out applications with multiple design options. Here, we discuss different outlooks consisting of performance and energy efficiency in cloud processors by running CloudSuite benchmarks as one of scale-out workloads. Experiment results on the CloudSuite benchmarks show that using STT-RAM memory compare to SRAM memory as last level cache, consumes less energy in L2 cache, around 59% at maximum.

CPU caches are powerful sources of information leakage. To develop practical cache-based attacks, the need for automation of the process of finding exploitable cachebased side-channels in computer systems is felt more than ever. cache template attack is a generic technique that utilizes Flush+Reload attack in order to automatically exploit cache vulnerability of Intel platforms. cache template attack on the T-table-based AES implementation consists of two phases including the pro, ling phase and key exploitation phase. Pro, ling is a preprocessing phase to monitor dependencies between the secret key and behavior of the cache memory. In addition, the addresses of T-tables can be obtained automatically. At the key exploitation phase, Most Significant Bits (MSBs) of the secret key bytes are retrieved by monitoring the exploitable addresses. This study proposed a simple yet effective searching technique, which accelerates the pro, ling phase by a factor of utmost 64. In order to verify the theoretical model of our technique, the mentioned attack on AES was implemented. The experimental results revealed that the pro, ling phase runtime of the cache template attack was approximately 10 minutes, while the proposed method could speed up the running of this phase up to almost 9 seconds.

Last level cache (LLC) management can considerably improve the performance of Chip Multi Processors (CMPs) by reducing the miss rate and decreasing the average L1 miss latency. LLC management approaches try to either map data to caches which are closer to cores, or exploit caches of neighboring cores to increase performance and reduce off-chip misses. To reduce the miss rate, we need to use cache slices of the other cores in NUCA architectures, but it increases the average L1 miss latency since the data to be accessed by cores are located in remote cache slices. As a result, designing an intelligent management approach to improve the system performance on a variety of workloads and systems is necessary. In this paper, an adaptive cache clustering called ACC is presented. ACC augments L2 cache size by using the L2 cache slices of neighboring cores adaptively. ACC selects cache slices with minimum distance to the target core while evaluating the amount of L2 cache slices being used on the surrounding tiles. To validate our approach, we apply several applications from SPEC CPU2006 and PARSEC benchmark suites. The results show the effectiveness of our approach, as we get speedup by up to 18%.

The modern processors that consist of large caches are very vulnerable to transient errors. Due to the importance of this problem, coding methods are adopted for protection against errors. The cost of reliability should be incurred to optimize the use of energy and area. This paper proposes an approach to dependability enhancement in unprotected caches of processors. For this purpose, the low-cost tag error mitigation mechanism is adopted to analyze the reliability of caches in modern processors. Benefiting from the tag Hamming distance increase technique, the proposed approach has a much lower overhead and decreases the false hit rate to zero.

Heroic literature of Wise of Toos (Firdausi) in his epic work, Shahnameh, is originated from its instinctive and integrated aesthetic language and interpretation as a literary text. Language of the work and interpretation technique of its creator-which is derived from his aesthetic mind- sometime may lead to polysemous texts, impressions and multiple interpretations by anagrams (puns). In the present study, by the aid of literal knowledge, we have dealt with stylistic analysis of illustrators’ various reports concerning to a hemistich from Shahnameh. Within the framework of those illustrations, the semantic linkage of the given hemistich has not been considered along the first part of this verse while ignoring this important point that verse second part is the complement and noting result of the first part and or it has been comprehended superficially and simply far from its deep concept.Study results indicate that through a new semantic stratum, Wise of Toos (poet) displays-by application of metaphor-allusion as a literary strategy-the most hidden archenemy of heroes i.e. self-deception or self-delusion like home foe; an opponent which trims hero’s body rigid in his mind in order to rob his life readily. By quoting a warning from a brave woman who has tested Young Sohrab once and found his weak point-and may not be sacrificed this time by delusion and fantasy of his deceitful self for stoutly body and power-as well as underlining this point that pride and self- satisfaction are deserved for a powerful chivalrous champion like Sohrab, Wise of Toos forewarns (premonition) the reader about Sohrab’s death due to his pride and naivety by a delicate style.